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4 commits
0.1 ... master

Author SHA1 Message Date
Gregor Riepl
f0e02bce8e All traces 0.5mm 2021-12-26 02:11:57 +01:00
Gregor Riepl
5841169524 Increased DIP40 holes to 1mm 2021-12-22 14:29:46 +01:00
Gregor Riepl
133ebacf2f Increased track width to 0.3mm 2021-12-12 13:54:56 +01:00
Gregor Riepl
435547f037 Added inverter to laser pwm out 2021-12-01 11:01:36 +01:00
4 changed files with 1727 additions and 1433 deletions

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@ -68,6 +68,31 @@ X 2 2 150 0 50 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Jumper_NC_Dual
#
DEF Device_Jumper_NC_Dual JP 0 30 Y N 1 F N
F0 "JP" 50 -100 50 H V L CNN
F1 "Device_Jumper_NC_Dual" 0 100 50 H V C BNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
SolderJumper*Bridged*
Jumper*
TestPoint*2Pads*
TestPoint*Bridge*
$ENDFPLIST
DRAW
A -60 10 64 386 1413 0 1 0 N -10 50 -110 50
A 60 10 64 386 1413 0 1 0 N 110 50 10 50
C -120 0 35 0 1 0 N
C 0 0 36 0 1 0 N
C 120 0 35 0 1 0 N
X 1 1 -250 0 95 R 50 50 0 1 P
X 2 2 0 -100 60 U 50 50 0 1 P
X 3 3 250 0 95 L 50 50 0 1 P
ENDDRAW
ENDDEF
#
# Device_Jumper_NC_Small
#
DEF Device_Jumper_NC_Small JP 0 30 N N 1 F N
@ -332,6 +357,38 @@ X 2 2 200 0 100 L 50 50 0 1 P
ENDDRAW
ENDDEF
#
# Transistor_FET_2N7002
#
DEF Transistor_FET_2N7002 Q 0 20 Y N 1 F N
F0 "Q" 200 75 50 H V L CNN
F1 "Transistor_FET_2N7002" 200 0 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-23" 200 -75 50 H I L CIN
F3 "" 0 0 50 H I L CNN
ALIAS 2N7002 2N7002E 2N7002H 2N7002K BS170F BS870 BSN20 BSS123 BSS127S DMG2302U DMG3402L DMG3404L DMG3406L DMG3414U DMG3418L DMN10H220L DMN10H700S DMN13H750S DMN2041L DMN2050L DMN2056U DMN2058U DMN2075U DMN2230U DMN24H11DS DMN24H3D5L DMN3042L DMN3051L DMN30H4D0L DMN3110S DMN3150L DMN3300U DMN3404L DMN6075S DMN6140L DMN67D7L DMN67D8L MMBF170 VN10LF ZVN3306F ZVN3310F ZVN3320F ZVN4106F ZXM61N02F ZXM61N03F ZXMN10A07F ZXMN2A01F ZXMN2A14F ZXMN2B01F ZXMN2B14FH ZXMN2F30FH ZXMN2F34FH ZXMN3A01F ZXMN3A14F ZXMN3B01F ZXMN3B14F ZXMN3F30FH ZXMN6A07F IRLML0030 IRLML2060 TSM2302CX AO3400A
$FPLIST
SOT?23*
$ENDFPLIST
DRAW
C 65 0 110 0 1 10 N
C 100 -70 10 0 1 0 F
C 100 70 10 0 1 0 F
P 2 0 1 0 10 0 -100 0 N
P 2 0 1 10 10 75 10 -75 N
P 2 0 1 10 30 -50 30 -90 N
P 2 0 1 10 30 20 30 -20 N
P 2 0 1 10 30 90 30 50 N
P 2 0 1 0 100 100 100 70 N
P 3 0 1 0 100 -100 100 0 30 0 N
P 4 0 1 0 30 -70 130 -70 130 70 30 70 N
P 4 0 1 0 40 0 80 15 80 -15 40 0 F
P 4 0 1 0 110 20 115 15 145 15 150 10 N
P 4 0 1 0 130 15 115 -10 145 -10 130 15 N
X G 1 -200 0 100 R 50 50 1 1 I
X S 2 100 -200 100 U 50 50 1 1 P
X D 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# oni_mbedLPC1768
#
DEF oni_mbedLPC1768 U 0 40 Y Y 1 F N

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@ -1,4 +1,4 @@
update=Sat 27 Nov 2021 14:25:53 CET
update=Wed 22 Dec 2021 14:51:30 CET
version=1
last_client=kicad
[general]
@ -28,8 +28,9 @@ MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.5
TrackWidth1=0.3
TrackWidth2=0.3
TrackWidth3=0.5
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
@ -228,8 +229,8 @@ Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
Clearance=0.3
TrackWidth=0.3
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
@ -237,3 +238,13 @@ uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

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