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3 commits
0.2 ... master

Author SHA1 Message Date
Gregor Riepl
f0e02bce8e All traces 0.5mm 2021-12-26 02:11:57 +01:00
Gregor Riepl
5841169524 Increased DIP40 holes to 1mm 2021-12-22 14:29:46 +01:00
Gregor Riepl
133ebacf2f Increased track width to 0.3mm 2021-12-12 13:54:56 +01:00
2 changed files with 962 additions and 1006 deletions

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@ -1,4 +1,4 @@
update=Sat 27 Nov 2021 14:25:53 CET
update=Wed 22 Dec 2021 14:51:30 CET
version=1
last_client=kicad
[general]
@ -28,8 +28,9 @@ MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.5
TrackWidth1=0.3
TrackWidth2=0.3
TrackWidth3=0.5
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
@ -228,8 +229,8 @@ Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
Clearance=0.3
TrackWidth=0.3
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
@ -237,3 +238,13 @@ uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1