3 commits

Author	SHA1	Message	Date
Gregor Riepl	7f742b2021	Added module library ... Fixed up schema with new part names Partial PCB redesign, incorporated schematic changes and errata Made PCB slightly smaller	2015-04-05 13:57:04 +02:00
Gregor Riepl	22a74a50ad	Updated large DB9 socket PCB with errata from schema	2015-04-03 17:04:03 +02:00
Gregor Riepl	d71b00987a	Added redesigned control board schema and PCB layout	2015-04-02 17:54:58 +02:00