Migrate to KiCad 6
This commit is contained in:
Gregor Riepl
parent
fa38e8d025
commit
8745848fd4
8 changed files with 18691 additions and 6701 deletions
1
.gitignore
vendored
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.gitignore
vendored
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@ -13,3 +13,4 @@
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plot/
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fp-info-cache
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*-bak
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*-backups
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@ -1,615 +0,0 @@
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EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# Connector_AVR-ISP-6
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#
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DEF Connector_AVR-ISP-6 J 0 40 Y Y 1 F N
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F0 "J" -250 450 50 H V L CNN
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F1 "Connector_AVR-ISP-6" 0 450 50 H V L CNN
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F2 "" -250 50 50 V I C CNN
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F3 "" -1275 -550 50 H I C CNN
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$FPLIST
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IDC?Header*2x03*
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Pin?Header*2x03*
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$ENDFPLIST
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DRAW
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S -105 -270 -95 -300 0 1 0 N
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S -105 400 -95 370 0 1 0 N
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S 300 -95 270 -105 0 1 0 N
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S 300 5 270 -5 0 1 0 N
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S 300 105 270 95 0 1 0 N
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S 300 205 270 195 0 1 0 N
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S 300 400 -300 -300 0 1 10 f
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X MISO 1 400 200 100 L 50 50 1 1 P
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X VCC 2 -100 500 100 D 50 50 1 1 P
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X SCK 3 400 0 100 L 50 50 1 1 P
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X MOSI 4 400 100 100 L 50 50 1 1 P
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X ~RST 5 400 -100 100 L 50 50 1 1 P
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X GND 6 -100 -400 100 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Connector_AVR-UPDI-6
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#
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DEF Connector_AVR-UPDI-6 J 0 40 Y Y 1 F N
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F0 "J" -250 350 50 H V L CNN
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F1 "Connector_AVR-UPDI-6" 0 350 50 H V L CNN
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F2 "" -250 -50 50 V I C CNN
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F3 "" -1275 -550 50 H I C CNN
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$FPLIST
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IDC?Header*2x03*
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Pin?Header*2x03*
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$ENDFPLIST
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DRAW
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S -105 -270 -95 -300 0 1 0 N
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S -105 300 -95 270 0 1 0 N
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S 300 105 270 95 0 1 0 N
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S 300 300 -300 -300 0 1 10 f
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X DATA 1 400 100 100 L 50 50 1 1 P
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X VCC 2 -100 400 100 D 50 50 1 1 P
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X NC 3 300 0 100 L 50 50 1 1 N N
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X NC 4 300 -100 100 L 50 50 1 1 N N
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X NC 5 300 -200 100 L 50 50 1 1 N N
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X GND 6 -100 -400 100 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Connector_Generic_Conn_01x02
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#
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DEF Connector_Generic_Conn_01x02 J 0 40 Y N 1 F N
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F0 "J" 0 100 50 H V C CNN
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F1 "Connector_Generic_Conn_01x02" 0 -200 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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Connector*:*_1x??_*
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$ENDFPLIST
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DRAW
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S -50 -95 0 -105 1 1 6 N
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S -50 5 0 -5 1 1 6 N
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S -50 50 50 -150 1 1 10 f
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X Pin_1 1 -200 0 150 R 50 50 1 1 P
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X Pin_2 2 -200 -100 150 R 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Connector_Generic_Conn_01x08
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#
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DEF Connector_Generic_Conn_01x08 J 0 40 Y N 1 F N
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F0 "J" 0 400 50 H V C CNN
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F1 "Connector_Generic_Conn_01x08" 0 -500 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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Connector*:*_1x??_*
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$ENDFPLIST
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DRAW
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S -50 -395 0 -405 1 1 6 N
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S -50 -295 0 -305 1 1 6 N
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S -50 -195 0 -205 1 1 6 N
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S -50 -95 0 -105 1 1 6 N
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S -50 5 0 -5 1 1 6 N
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S -50 105 0 95 1 1 6 N
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S -50 205 0 195 1 1 6 N
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S -50 305 0 295 1 1 6 N
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S -50 350 50 -450 1 1 10 f
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X Pin_1 1 -200 300 150 R 50 50 1 1 P
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X Pin_2 2 -200 200 150 R 50 50 1 1 P
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X Pin_3 3 -200 100 150 R 50 50 1 1 P
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X Pin_4 4 -200 0 150 R 50 50 1 1 P
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X Pin_5 5 -200 -100 150 R 50 50 1 1 P
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X Pin_6 6 -200 -200 150 R 50 50 1 1 P
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X Pin_7 7 -200 -300 150 R 50 50 1 1 P
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X Pin_8 8 -200 -400 150 R 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_C
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#
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DEF Device_C C 0 10 N Y 1 F N
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F0 "C" 25 100 50 H V L CNN
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F1 "Device_C" 25 -100 50 H V L CNN
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F2 "" 38 -150 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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C_*
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$ENDFPLIST
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DRAW
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P 2 0 1 20 -80 -30 80 -30 N
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P 2 0 1 20 -80 30 80 30 N
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X ~ 1 0 150 110 D 50 50 1 1 P
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X ~ 2 0 -150 110 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_CP
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#
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DEF Device_CP C 0 10 N Y 1 F N
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F0 "C" 25 100 50 H V L CNN
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F1 "Device_CP" 25 -100 50 H V L CNN
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F2 "" 38 -150 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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CP_*
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$ENDFPLIST
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DRAW
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S -90 20 90 40 0 1 0 N
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S 90 -20 -90 -40 0 1 0 F
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P 2 0 1 0 -70 90 -30 90 N
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P 2 0 1 0 -50 110 -50 70 N
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X ~ 1 0 150 110 D 50 50 1 1 P
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X ~ 2 0 -150 110 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_Crystal
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#
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DEF Device_Crystal Y 0 40 N N 1 F N
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F0 "Y" 0 150 50 H V C CNN
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F1 "Device_Crystal" 0 -150 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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Crystal*
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$ENDFPLIST
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DRAW
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S -45 100 45 -100 0 1 12 N
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P 2 0 1 0 -100 0 -75 0 N
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P 2 0 1 20 -75 -50 -75 50 N
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P 2 0 1 20 75 -50 75 50 N
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P 2 0 1 0 100 0 75 0 N
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X 1 1 -150 0 50 R 50 50 1 1 P
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X 2 2 150 0 50 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_D_Zener
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#
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DEF Device_D_Zener D 0 40 N N 1 F N
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F0 "D" 0 100 50 H V C CNN
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F1 "Device_D_Zener" 0 -100 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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TO-???*
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*_Diode_*
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*SingleDiode*
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D_*
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$ENDFPLIST
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DRAW
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P 2 0 1 0 50 0 -50 0 N
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P 3 0 1 10 -50 -50 -50 50 -30 50 N
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P 4 0 1 10 50 -50 50 50 -50 0 50 -50 N
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X K 1 -150 0 100 R 50 50 1 1 P
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X A 2 150 0 100 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_Q_NMOS_GDS
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#
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DEF Device_Q_NMOS_GDS Q 0 0 Y N 1 F N
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F0 "Q" 200 50 50 H V L CNN
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F1 "Device_Q_NMOS_GDS" 200 -50 50 H V L CNN
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F2 "" 200 100 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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C 65 0 110 0 1 10 N
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C 100 -70 10 0 1 0 F
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C 100 70 10 0 1 0 F
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P 2 0 1 0 10 0 -100 0 N
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P 2 0 1 10 10 75 10 -75 N
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P 2 0 1 10 30 -50 30 -90 N
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P 2 0 1 10 30 20 30 -20 N
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P 2 0 1 10 30 90 30 50 N
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P 2 0 1 0 100 100 100 70 N
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P 3 0 1 0 100 -100 100 0 30 0 N
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P 4 0 1 0 30 -70 130 -70 130 70 30 70 N
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P 4 0 1 0 40 0 80 15 80 -15 40 0 F
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P 4 0 1 0 110 20 115 15 145 15 150 10 N
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P 4 0 1 0 130 15 115 -10 145 -10 130 15 N
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X G 1 -200 0 100 R 50 50 1 1 I
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X D 2 100 200 100 D 50 50 1 1 P
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X S 3 100 -200 100 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_Q_NPN_BEC
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#
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DEF Device_Q_NPN_BEC Q 0 0 Y N 1 F N
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F0 "Q" 200 50 50 H V L CNN
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F1 "Device_Q_NPN_BEC" 200 -50 50 H V L CNN
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F2 "" 200 100 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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C 50 0 111 0 1 10 N
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P 2 0 1 0 25 25 100 100 N
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P 3 0 1 0 25 -25 100 -100 100 -100 N
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P 3 0 1 20 25 75 25 -75 25 -75 N
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P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
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X B 1 -200 0 225 R 50 50 1 1 I
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X E 2 100 -200 100 U 50 50 1 1 P
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X C 3 100 200 100 D 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_Q_PNP_BCE
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#
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DEF Device_Q_PNP_BCE Q 0 0 Y N 1 F N
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F0 "Q" 200 50 50 H V L CNN
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F1 "Device_Q_PNP_BCE" 200 -50 50 H V L CNN
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F2 "" 200 100 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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C 50 0 111 0 1 10 N
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P 2 0 1 0 25 25 100 100 N
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P 3 0 1 0 25 -25 100 -100 100 -100 N
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P 3 0 1 20 25 75 25 -75 25 -75 N
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P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
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X B 1 -200 0 225 R 50 50 1 1 I
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X C 2 100 200 100 D 50 50 1 1 P
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X E 3 100 -200 100 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_Q_PNP_BEC
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#
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DEF Device_Q_PNP_BEC Q 0 0 Y N 1 F N
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F0 "Q" 200 50 50 H V L CNN
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F1 "Device_Q_PNP_BEC" 200 -50 50 H V L CNN
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F2 "" 200 100 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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C 50 0 111 0 1 10 N
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P 2 0 1 0 25 25 100 100 N
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P 3 0 1 0 25 -25 100 -100 100 -100 N
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P 3 0 1 20 25 75 25 -75 25 -75 N
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P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
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X B 1 -200 0 225 R 50 50 1 1 I
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X E 2 100 -200 100 U 50 50 1 1 P
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X C 3 100 200 100 D 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_R
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#
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DEF Device_R R 0 0 N Y 1 F N
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F0 "R" 80 0 50 V V C CNN
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F1 "Device_R" 0 0 50 V V C CNN
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F2 "" -70 0 50 V I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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R_*
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$ENDFPLIST
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DRAW
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S -40 -100 40 100 0 1 10 N
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X ~ 1 0 150 50 D 50 50 1 1 P
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X ~ 2 0 -150 50 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Diode_Bridge_MB6S
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#
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DEF Diode_Bridge_MB6S D 0 0 Y Y 1 F N
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F0 "D" 100 275 50 H V L CNN
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F1 "Diode_Bridge_MB6S" 100 200 50 H V L CNN
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F2 "Package_TO_SOT_SMD:TO-269AA" 150 125 50 H I L CNN
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F3 "" 0 0 50 H I C CNN
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ALIAS MB4S MB6S RMB2S RMB4S
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$FPLIST
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TO?269AA*
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$ENDFPLIST
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DRAW
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P 2 0 1 0 -100 150 -50 100 N
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P 2 0 1 0 -50 -100 -100 -150 N
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P 2 0 1 0 100 -50 150 -100 N
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P 2 0 1 0 100 50 150 100 N
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P 4 0 1 0 -150 100 -100 50 -75 125 -150 100 N
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P 4 0 1 0 -100 -50 -150 -100 -75 -125 -100 -50 N
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P 4 0 1 0 50 100 100 150 125 75 50 100 N
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P 4 0 1 0 125 -75 50 -100 100 -150 125 -75 N
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P 5 0 1 0 -200 0 0 -200 200 0 0 200 -200 0 N
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X ~~ 1 0 -300 100 U 50 50 1 1 P
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X ~~ 2 0 300 100 D 50 50 1 1 P
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X + 3 300 0 100 L 50 50 1 1 P
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X - 4 -300 0 100 R 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Graphic_Logo_Open_Hardware_Small
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#
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DEF Graphic_Logo_Open_Hardware_Small #LOGO 0 40 Y Y 1 F N
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F0 "#LOGO" 0 275 50 H I C CNN
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F1 "Graphic_Logo_Open_Hardware_Small" 0 -225 50 H I C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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P 277 0 1 0 132 -171 130 -170 125 -167 118 -162 109 -156 100 -150 93 -146 88 -142 86 -141 85 -142 81 -144 75 -147 71 -149 66 -151 63 -151 63 -151 61 -147 58 -139 53 -130 49 -119 44 -107 38 -95 34 -83 29 -72 26 -64 24 -58 23 -55 23 -55 26 -52 31 -49 41 -40 51 -27 57 -13 60 3 58 18 52 32 42 45 30 54 16 60 0 62 -15 61 -29 55 -42 45 -48 39 -55 26 -60 12 -60 9 -59 -7 -55 -21 -47 -34 -36 -45 -34 -46 -29 -50 -25 -53 -23 -55 -42 -102 -45 -110 -51 -123 -55 -134 -59 -143 -62 -149 -63 -151 -63 -151 -65 -151 -68 -150 -75 -147 -79 -145 -84 -142 -87 -141 -89 -142 -93 -145 -100 -150 -109 -156 -117 -161 -124 -166 -130 -170 -132 -171 -133 -171 -135 -170 -139 -166 -146 -160 -155 -151 -156 -150 -164 -142 -170 -136 -174 -131 -175 -129 -175 -129 -174 -127 -170 -121 -166 -114 -160 -105 -144 -82 -153 -61 -155 -54 -159 -46 -161 -41 -162 -38 -165 -37 -170 -36 -179 -34 -189 -32 -199 -31 -207 -29 -214 -28 -217 -27 -217 -27 -218 -25 -218 -22 -218 -17 -219 -9 -219 3 -219 5 -218 16 -218 25 -218 30 -218 33 -218 33 -215 33 -209 35 -200 36 -190 38 -189 39 -179 41 -170 42 -164 44 -161 45 -161 45 -159 49 -156 56 -152 64 -149 72 -146 79 -144 85 -143 87 -143 87 -145 90 -148 95 -153 102 -160 111 -160 112 -166 121 -171 128 -174 133 -175 136 -175 136 -173 138 -169 143 -162 150 -155 158 -152 160 -144 169 -138 174 -134 177 -132 178 -132 178 -130 176 -124 172 -117 167 -108 161 -107 161 -98 155 -91 150 -86 146 -84 145 -83 145 -80 146 -73 148 -66 151 -58 155 -50 158 -45 160 -42 162 -42 162 -41 165 -40 171 -38 180 -36 191 -35 193 -33 203 -32 212 -31 218 -30 220 -28 221 -23 221 -16 221 -6 221 3 221 13 221 21 221 27 220 29 220 29 220 30 217 32 210 33 201 36 190 36 188 38 178 40 169 41 163 42 161 42 161 47 159 54 156 62 152 82 144 107 161 109 163 118 169 125 174 130 177 133 178 133 178 135 176 140 171 147 165 154 157 160 151 167 144 171 140 174 137 174 135 174 134 173 131 169 126 164 118 158 110 153 102 148 94 144 88 143 85 143 84 145 79 148 72 152 63 160 44 173 41 181 40 192 38 202 36 218 33 219 -26 216 -27 214 -27 208 -29 199 -30 189 -32 181 -34 172 -36 166 -37 163 -37 162 -38 160 -42 157 -49 154 -57 150 -65 147 -73 145 -79 144 -82 145 -84 149 -89 153 -97 159 -105 165 -114 170 -121 173 -126 175 -129 174 -131 171 -135 164 -141 155 -151 153 -152 145 -160 139 -166 134 -170 132 -171 F
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ENDDRAW
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ENDDEF
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#
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# Isolator_TLP785
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#
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DEF Isolator_TLP785 U 0 40 Y Y 1 F N
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F0 "U" -200 200 50 H V L CNN
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F1 "Isolator_TLP785" 0 200 50 H V L CNN
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F2 "Package_DIP:DIP-4_W7.62mm" -200 -200 50 H I L CIN
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F3 "" 0 0 50 H I L CNN
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ALIAS SFH617A-1 SFH617A-2 SFH617A-3 SFH617A-4 SFH617A-1X001 SFH617A-2X001 SFH617A-3X001 SFH617A-4X001
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$FPLIST
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DIP*W7.62mm*
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$ENDFPLIST
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DRAW
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S -200 150 200 -150 0 1 10 f
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P 2 0 1 10 -125 -25 -75 -25 N
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P 2 0 1 0 100 25 175 100 N
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P 2 0 1 0 175 -100 100 -25 F
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P 2 0 1 0 175 -100 200 -100 N
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P 2 0 1 0 175 100 200 100 N
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P 3 0 1 0 -100 -25 -100 -100 -200 -100 N
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P 3 0 1 20 100 75 100 -75 100 -75 N
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P 4 0 1 0 -200 100 -100 100 -100 -50 -100 25 N
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P 4 0 1 10 -100 -25 -125 25 -75 25 -100 -25 N
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P 5 0 1 0 -20 -20 30 -20 15 -25 15 -15 30 -20 N
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P 5 0 1 0 -20 20 30 20 15 15 15 25 30 20 N
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P 5 0 1 0 120 -65 140 -45 160 -85 120 -65 120 -65 F
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X ~ 1 -300 100 100 R 50 50 1 1 P
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X ~ 2 -300 -100 100 R 50 50 1 1 P
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X ~ 3 300 -100 100 L 50 50 1 1 P
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X ~ 4 300 100 100 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# MCU_Microchip_ATtiny_ATtiny814-SS
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#
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DEF MCU_Microchip_ATtiny_ATtiny814-SS U 0 20 Y Y 1 F N
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F0 "U" -500 650 50 H V L BNN
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F1 "MCU_Microchip_ATtiny_ATtiny814-SS" 100 -650 50 H V L TNN
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F2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" 0 0 50 H I C CIN
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F3 "" 0 0 50 H I C CNN
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ALIAS ATtiny404-SS ATtiny804-SS ATtiny1604-SS ATtiny214-SS ATtiny414-SS ATtiny814-SS ATtiny1614-SS
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$FPLIST
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SOIC*3.9x8.7mm*P1.27mm*
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$ENDFPLIST
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DRAW
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S -500 -600 500 600 0 1 10 f
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X VCC 1 0 700 100 D 50 50 1 1 W
|
||||
X ~RESET~/PA0 10 600 400 100 L 50 50 1 1 B
|
||||
X PA1 11 600 300 100 L 50 50 1 1 B
|
||||
X PA2 12 600 200 100 L 50 50 1 1 B
|
||||
X PA3 13 600 100 100 L 50 50 1 1 B
|
||||
X GND 14 0 -700 100 U 50 50 1 1 W
|
||||
X PA4 2 600 0 100 L 50 50 1 1 B
|
||||
X PA5 3 600 -100 100 L 50 50 1 1 B
|
||||
X PA6 4 600 -200 100 L 50 50 1 1 B
|
||||
X PA7 5 600 -300 100 L 50 50 1 1 B
|
||||
X PB3 6 -600 100 100 R 50 50 1 1 B
|
||||
X PB2 7 -600 200 100 R 50 50 1 1 B
|
||||
X PB1 8 -600 300 100 R 50 50 1 1 B
|
||||
X PB0 9 -600 400 100 R 50 50 1 1 B
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# MCU_Microchip_ATtiny_ATtiny84A-SSU
|
||||
#
|
||||
DEF MCU_Microchip_ATtiny_ATtiny84A-SSU U 0 20 Y Y 1 F N
|
||||
F0 "U" -500 850 50 H V L BNN
|
||||
F1 "MCU_Microchip_ATtiny_ATtiny84A-SSU" 100 -850 50 H V L TNN
|
||||
F2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" 0 0 50 H I C CIN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
ALIAS ATtiny24-20SSU ATtiny24A-SSU ATtiny44V-10SSU ATtiny44-20SSU ATtiny44A-SSU ATtiny84V-10SSU ATtiny84-20SSU ATtiny84A-SSU
|
||||
$FPLIST
|
||||
SOIC*3.9x8.7mm*P1.27mm*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -500 -800 500 800 0 1 10 f
|
||||
X VCC 1 0 900 100 D 50 50 1 1 W
|
||||
X PA3 10 600 300 100 L 50 50 1 1 B
|
||||
X PA2 11 600 400 100 L 50 50 1 1 B
|
||||
X PA1 12 600 500 100 L 50 50 1 1 B
|
||||
X AREF/PA0 13 600 600 100 L 50 50 1 1 B
|
||||
X GND 14 0 -900 100 U 50 50 1 1 W
|
||||
X XTAL1/PB0 2 600 -300 100 L 50 50 1 1 B
|
||||
X XTAL2/PB1 3 600 -400 100 L 50 50 1 1 B
|
||||
X ~RESET~/PB3 4 600 -600 100 L 50 50 1 1 B
|
||||
X PB2 5 600 -500 100 L 50 50 1 1 B
|
||||
X PA7 6 600 -100 100 L 50 50 1 1 B
|
||||
X PA6 7 600 0 100 L 50 50 1 1 B
|
||||
X PA5 8 600 100 100 L 50 50 1 1 B
|
||||
X PA4 9 600 200 100 L 50 50 1 1 B
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Mechanical_MountingHole
|
||||
#
|
||||
DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
|
||||
F0 "H" 0 200 50 H V C CNN
|
||||
F1 "Mechanical_MountingHole" 0 125 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
MountingHole*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C 0 0 50 0 1 50 N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Regulator_Linear_LM2937xMP
|
||||
#
|
||||
DEF Regulator_Linear_LM2937xMP U 0 10 Y Y 1 F N
|
||||
F0 "U" -150 125 50 H V C CNN
|
||||
F1 "Regulator_Linear_LM2937xMP" 0 125 50 H V L CNN
|
||||
F2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" 0 225 50 H I C CIN
|
||||
F3 "" 0 -50 50 H I C CNN
|
||||
ALIAS SPX2920M3-5.0_SOT223 LT1129-3.3_SOT223 LT1129-5.0_SOT223 LM2937xMP AP7361C-10E AP7361C-12E AP7361C-15E AP7361C-18E AP7361C-25E AP7361C-28E AP7361C-33E
|
||||
$FPLIST
|
||||
SOT?223*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -200 -200 200 75 0 1 10 f
|
||||
X VI 1 -300 0 100 R 50 50 1 1 W
|
||||
X GND 2 0 -300 100 U 50 50 1 1 W
|
||||
X VO 3 300 0 100 L 50 50 1 1 w
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Transistor_BJT_MMBT3906
|
||||
#
|
||||
DEF Transistor_BJT_MMBT3906 Q 0 0 Y N 1 F N
|
||||
F0 "Q" 200 75 50 H V L CNN
|
||||
F1 "Transistor_BJT_MMBT3906" 200 0 50 H V L CNN
|
||||
F2 "Package_TO_SOT_SMD:SOT-23" 200 -75 50 H I L CIN
|
||||
F3 "" 0 0 50 H I L CNN
|
||||
ALIAS BC808 BC856 BC857 BC858 BC859 BC860 MMBT3906
|
||||
$FPLIST
|
||||
SOT?23*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C 50 0 111 0 1 10 N
|
||||
P 2 0 1 0 25 25 100 100 N
|
||||
P 3 0 1 0 25 -25 100 -100 100 -100 N
|
||||
P 3 0 1 20 25 75 25 -75 25 -75 N
|
||||
P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
|
||||
X B 1 -200 0 225 R 50 50 1 1 I
|
||||
X E 2 100 -200 100 U 50 50 1 1 P
|
||||
X C 3 100 200 100 D 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Transistor_FET_FDS6630A
|
||||
#
|
||||
DEF Transistor_FET_FDS6630A Q 0 20 Y N 1 F N
|
||||
F0 "Q" 200 100 50 H V L CNN
|
||||
F1 "Transistor_FET_FDS6630A" 200 0 50 H V L CNN
|
||||
F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 200 -100 50 H I L CNN
|
||||
F3 "" 0 0 50 H I L CNN
|
||||
ALIAS IRF7403 FDS2734 FDS6630A Si4162DY
|
||||
$FPLIST
|
||||
SOIC*3.9x4.9mm*P1.27mm*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C 65 0 110 0 1 10 N
|
||||
C 100 -70 10 0 1 0 F
|
||||
C 100 70 10 0 1 0 F
|
||||
P 2 0 1 0 10 0 -100 0 N
|
||||
P 2 0 1 10 10 75 10 -75 N
|
||||
P 2 0 1 10 30 -50 30 -90 N
|
||||
P 2 0 1 10 30 20 30 -20 N
|
||||
P 2 0 1 10 30 90 30 50 N
|
||||
P 2 0 1 0 100 100 100 70 N
|
||||
P 3 0 1 0 100 -100 100 0 30 0 N
|
||||
P 4 0 1 0 30 -70 130 -70 130 70 30 70 N
|
||||
P 4 0 1 0 40 0 80 15 80 -15 40 0 F
|
||||
P 4 0 1 0 110 20 115 15 145 15 150 10 N
|
||||
P 4 0 1 0 130 15 115 -10 145 -10 130 15 N
|
||||
X S 1 100 -200 100 U 50 50 1 1 P
|
||||
X S 2 100 -200 100 U 50 50 1 1 P N
|
||||
X S 3 100 -200 100 U 50 50 1 1 P N
|
||||
X G 4 -200 0 100 R 50 50 1 1 I
|
||||
X D 5 100 200 100 D 50 50 1 1 P N
|
||||
X D 6 100 200 100 D 50 50 1 1 P N
|
||||
X D 7 100 200 100 D 50 50 1 1 P N
|
||||
X D 8 100 200 100 D 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_+24V
|
||||
#
|
||||
DEF power_+24V #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_+24V" 0 140 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +24V 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_+5V
|
||||
#
|
||||
DEF power_+5V #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_+5V" 0 140 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +5V 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_+VSW
|
||||
#
|
||||
DEF power_+VSW #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_+VSW" 0 140 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +VSW 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_-VSW
|
||||
#
|
||||
DEF power_-VSW #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 100 50 H I C CNN
|
||||
F1 "power_-VSW" 0 150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
|
||||
X -VSW 1 0 0 0 U 50 50 0 0 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_GND
|
||||
#
|
||||
DEF power_GND #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -250 50 H I C CNN
|
||||
F1 "power_GND" 0 -150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
|
||||
X GND 1 0 0 0 D 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_GNDA
|
||||
#
|
||||
DEF power_GNDA #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -250 50 H I C CNN
|
||||
F1 "power_GNDA" 0 -150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
|
||||
X GNDA 1 0 0 0 D 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_VAA
|
||||
#
|
||||
DEF power_VAA #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_VAA" 0 150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X VAA 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
16536
ledstrip.kicad_pcb
16536
ledstrip.kicad_pcb
File diff suppressed because it is too large
Load diff
75
ledstrip.kicad_prl
Normal file
75
ledstrip.kicad_prl
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
{
|
||||
"board": {
|
||||
"active_layer": 0,
|
||||
"active_layer_preset": "",
|
||||
"auto_track_width": true,
|
||||
"hidden_nets": [],
|
||||
"high_contrast_mode": 0,
|
||||
"net_color_mode": 1,
|
||||
"opacity": {
|
||||
"pads": 1.0,
|
||||
"tracks": 1.0,
|
||||
"vias": 1.0,
|
||||
"zones": 0.6
|
||||
},
|
||||
"ratsnest_display_mode": 0,
|
||||
"selection_filter": {
|
||||
"dimensions": true,
|
||||
"footprints": true,
|
||||
"graphics": true,
|
||||
"keepouts": true,
|
||||
"lockedItems": true,
|
||||
"otherItems": true,
|
||||
"pads": true,
|
||||
"text": true,
|
||||
"tracks": true,
|
||||
"vias": true,
|
||||
"zones": true
|
||||
},
|
||||
"visible_items": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
29,
|
||||
30,
|
||||
32,
|
||||
33,
|
||||
34,
|
||||
35,
|
||||
36
|
||||
],
|
||||
"visible_layers": "000ffff_80000001",
|
||||
"zone_display_mode": 0
|
||||
},
|
||||
"meta": {
|
||||
"filename": "ledstrip.kicad_prl",
|
||||
"version": 3
|
||||
},
|
||||
"project": {
|
||||
"files": []
|
||||
}
|
||||
}
|
||||
433
ledstrip.kicad_pro
Normal file
433
ledstrip.kicad_pro
Normal file
|
|
@ -0,0 +1,433 @@
|
|||
{
|
||||
"board": {
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.049999999999999996,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.09999999999999999,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 0.762,
|
||||
"height": 1.524,
|
||||
"width": 1.524
|
||||
},
|
||||
"silk_line_width": 0.12,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.15,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"45_degree_only": false,
|
||||
"min_clearance": 0.5
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"filename": "board_design_settings.json",
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"copper_edge_clearance": "error",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint_type_mismatch": "error",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "error",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zone_has_empty_net": "error",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rule_severitieslegacy_courtyards_overlap": true,
|
||||
"rule_severitieslegacy_no_courtyard_defined": false,
|
||||
"rules": {
|
||||
"allow_blind_buried_vias": false,
|
||||
"allow_microvias": false,
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_copper_edge_clearance": 0.024999999999999998,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.19999999999999998,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_diameter": 0.39999999999999997,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"track_widths": [
|
||||
0.0,
|
||||
2.0
|
||||
],
|
||||
"via_dimensions": [
|
||||
{
|
||||
"diameter": 0.0,
|
||||
"drill": 0.0
|
||||
},
|
||||
{
|
||||
"diameter": 2.0,
|
||||
"drill": 1.6
|
||||
}
|
||||
],
|
||||
"zones_allow_external_fillets": false,
|
||||
"zones_use_no_outline": true
|
||||
},
|
||||
"layer_presets": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
]
|
||||
],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_label_syntax": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "ledstrip.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.25,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"net_colors": null
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"drawing": {
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.25,
|
||||
"pin_symbol_size": 0.0,
|
||||
"text_offset_ratio": 0.08
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "Pcbnew",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"fix_passive_vals": false,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 0,
|
||||
"workbook_filename": ""
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_adjust_passive_values": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"fbe8ebfc-2a8e-4eb8-85c5-38ddeaa5dd00",
|
||||
""
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
5701
ledstrip.kicad_sch
Normal file
5701
ledstrip.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
251
ledstrip.pro
251
ledstrip.pro
|
|
@ -1,251 +0,0 @@
|
|||
update=Sat 22 Jan 2022 21:48:50 CET
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.2
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.25
|
||||
TrackWidth2=2
|
||||
ViaDiameter1=0.8
|
||||
ViaDrill1=0.4
|
||||
ViaDiameter2=2
|
||||
ViaDrill2=1.6
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.12
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.2
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.4
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
1776
ledstrip.sch
1776
ledstrip.sch
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue