seto/petmem
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  • 82a00c720e Simplify address comment main v5 Gregor Riepl 2024-09-29 23:59:02 +0200
  • a70d759aef Finetuning Gregor Riepl 2024-09-29 12:45:00 +0200
  • ba983ad9da Removed some extras and finished routing PCB Gregor Riepl 2024-09-28 22:15:21 +0200
  • b1dd0f0aaf Added UART lib ROM, addr logic and placed ICs Gregor Riepl 2024-09-09 12:35:14 +0200
  • cb53088da3 Revert back to SOP-28 Gregor Riepl 2024-09-06 09:22:57 +0200
  • e915f888f8 PCB with DIP-28 SRAM v4-dip Gregor Riepl 2024-09-06 09:21:51 +0200
  • 9229cef954 Drop excluded parts from BOM v4-sop Gregor Riepl 2024-09-04 07:46:42 +0200
  • d3379170c1 Refresh schema and PCB, remove obsolete sections Gregor Riepl 2024-09-04 07:33:55 +0200
  • e6ca30ddba Routed 62c2256 RAM, added speaker Gregor Riepl 2024-03-13 08:19:07 +0100
  • ae654de79a wip v4 variant Gregor Riepl 2024-03-10 14:44:15 +0100
  • 5ab7d36e3a Group blocks in schematic v3 Gregor Riepl 2024-03-10 13:30:34 +0100
  • aaa309abfe Add HCT10 option to reduce propagation delay Gregor Riepl 2024-03-09 11:22:57 +0100
  • b814979dab CE should depend on phi2 Gregor Riepl 2024-03-06 23:56:51 +0100
  • 1a9320a034 Add test points, reorder reset header Gregor Riepl 2024-03-02 23:58:15 +0100
  • 68d7e86e99 Layout Gregor Riepl 2024-02-08 01:33:47 +0100
  • aab0e2b974 Added pulse generator to WR pin Gregor Riepl 2024-02-08 01:32:12 +0100
  • 5dbada7773 Add measurements and comment about connectors v2 Gregor Riepl 2023-11-12 22:06:23 +0100
  • 30086b7cfd Update sheet versions Gregor Riepl 2023-11-12 21:53:52 +0100
  • 01487a4c75 Correct pinout for PET mem interface Gregor Riepl 2023-11-12 21:51:37 +0100
  • 01de5ae605 Ignore plot output Gregor Riepl 2023-11-12 21:51:13 +0100
  • 286b80476c Enlarged vias for cnc production v1 Gregor Riepl 2023-10-17 23:43:20 +0200
  • 5cb86b57ba Reposition silk screen Gregor Riepl 2023-10-17 23:01:18 +0200
  • b484a0842c Add sheet descriptions, make some vias more accessible Gregor Riepl 2023-10-13 21:22:23 +0200
  • 22778fce4f Designate power connector same as on main board Gregor Riepl 2023-10-13 14:08:04 +0200
  • e20ca7fe49 Add 5V regulator Gregor Riepl 2023-10-13 14:04:56 +0200
  • 5f8c386c82 Gate out A15 Gregor Riepl 2023-10-13 11:53:55 +0200
  • adcadc5eec Relayout to reduce crossing Gregor Riepl 2023-10-13 11:04:36 +0200
  • 741f704ef9 Initial checkin Gregor Riepl 2023-10-13 09:27:04 +0200