From 2ebbbd74684f2a39cd16658ef0a61bb94f0a34c6 Mon Sep 17 00:00:00 2001 From: Gregor Riepl Date: Sun, 4 Sep 2022 10:02:27 +0200 Subject: [PATCH] Split out test driver into driver2 --- driver.a65 | 101 ---------------------------------- driver2.a65 | 154 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 154 insertions(+), 101 deletions(-) create mode 100644 driver2.a65 diff --git a/driver.a65 b/driver.a65 index be67db3..db68dab 100644 --- a/driver.a65 +++ b/driver.a65 @@ -50,10 +50,6 @@ BAUD_RATE = 600 ; entry points .code - ; for development and testing - .export rs_test - rs_test: - jmp test ; these are convenience entry points right at the beginning of the page, ; to reduce dependency on code size. ; relocatable code would be perfect, but that's a lot more work. @@ -99,103 +95,6 @@ BAUD_RATE = 600 ; main code follows .code -;FIXME BEGIN - ; test code: - ; single-byte RS-232 transmission - ; this code runs asynchronously in a VIA T2 interrupt handler - ; the handler is installed and uninstalled automatically until - ; transmission is complete. - ; do not call this too quickly in succession, or you will lock - ; up the CPU in an endless loop. - test: - sei - - lda #10 - sta rs_available - lda rs_data - asl a - sta rs_data - lda #%00000001 - rol a - sta rs_data+1 - - lda VIA_DDRB - ora #%00001000 - sta VIA_DDRB - - lda IRQVec - ldx IRQVec+1 - sta oldvector - stx oldvector+1 - lda #irqtest - sta IRQVec - stx IRQVec+1 - - lda VIA_CR - and #%11011111 - sta VIA_CR - lda #%10100000 - sta VIA_IER - testperiod = PHI2_CLOCK/BAUD_RATE - lda #testperiod - sta VIA_T2CL - stx VIA_T2CH - rts - - cli - rts - - irqtest: - sei - cld - pha - txa - pha - - lda VIA_IFR - and #%00100000 - beq @irqtestend - - ldx rs_available - beq @irqtestrestore - dex - stx rs_available - - ;lda #testperiod - ;sta VIA_T2CL - stx VIA_T2CH - - lsr rs_data+1 - ror rs_data - lda VIA_PB - bcc @irqtestblank - ora #%00001000 - bcs @irqtestwrite - @irqtestblank: - and #%11110111 - @irqtestwrite: - sta VIA_PB - - @irqtestend: - pla - tax - pla - jmp (oldvector) - - @irqtestrestore: - lda #%00100000 - sta VIA_IER - lda oldvector - ldx oldvector+1 - sta IRQVec - stx IRQVec+1 - clv - bvc @irqtestend -;FIXME END - ; driver installation, must be called once to set up IRQs, etc. install: ; FIXME this doesn't work if we're loading from ROM diff --git a/driver2.a65 b/driver2.a65 new file mode 100644 index 0000000..6239025 --- /dev/null +++ b/driver2.a65 @@ -0,0 +1,154 @@ + +; 6502 mode +.p02 + +; load useful register/memory locations +.include "pet.inc" + +; for some reason, the PIA registers are missing in pet.inc... +PIA1 := $E810 +PIA1_PA := PIA1+$0 ; PORT A or DDR A: Data Direction Register A +PIA1_CRA := PIA1+$1 ; CRA: Control Register A +PIA1_PB := PIA1+$2 ; PORT B or DDR B: Data Direction Register B +PIA1_CRB := PIA1+$3 ; CRB: Control Register B +PIA2 := $E820 +PIA2_PA := PIA2+$0 +PIA2_CRA := PIA2+$1 +PIA2_PB := PIA2+$2 +PIA2_CRB := PIA2+$3 + +; 1MHz phase2 clock +PHI2_CLOCK = 1000000 +; don't set the baud rate too high, or other operations will be starved +BAUD_RATE = 600 + +; parameters and return values can reside in an unused area of the zero page +.zeropage + ; used as the shift register counter + .export rs_available + rs_available: .byte 0 + ; shift register + .export rs_data + rs_data: .word 0 + ; saved old interrupt vector + .export rs_vector + rs_vector: .word 0 + +; this is for the load address, so we can generate PRG files. +; works as long as the code segment comes right after these two bytes, +; i.e. as long as the LOADADDR segment resides at $load_address - 2 +.segment "LOADADDR" + .export LOADADDR + LOADADDR: + .word *+2 + +; test code follows +.code + + ; test code: + ; single-byte RS-232 transmission + ; this code runs asynchronously in a VIA T2 interrupt handler + ; the handler is installed and uninstalled automatically until + ; transmission is complete. + ; do not call this too quickly in succession, or you will lock + ; up the CPU in an endless loop. + + testperiod = PHI2_CLOCK/BAUD_RATE + + test: + sei + + lda IRQVec + cmp irqtest + bne @testok + lda IRQVec+1 + cmp irqtest+1 + beq @testend + + @testok: + lda #10 + sta rs_available + lda rs_data + asl a + sta rs_data + lda #%00000001 + rol a + sta rs_data+1 + + lda VIA_DDRB + ora #%00001000 + sta VIA_DDRB + + lda IRQVec + ldx IRQVec+1 + sta rs_vector + stx rs_vector+1 + lda #irqtest + sta IRQVec + stx IRQVec+1 + + lda VIA_CR + and #%11011111 + sta VIA_CR + lda #%10100000 + sta VIA_IER + lda #testperiod + sta VIA_T2CL + stx VIA_T2CH + + @testend: + cli + rts + + irqtest: + sei + cld + pha + txa + pha + + lda VIA_IFR + and #%00100000 + beq @irqtestend + + ldx rs_available + beq @irqtestrestore + dex + stx rs_available + + ;lda #testperiod + ;sta VIA_T2CL + stx VIA_T2CH + + lsr rs_data+1 + ror rs_data + lda VIA_PB + bcc @irqtestblank + ora #%00001000 + bcs @irqtestwrite + @irqtestblank: + and #%11110111 + @irqtestwrite: + sta VIA_PB + + @irqtestend: + pla + tax + pla + jmp (rs_vector) + + @irqtestrestore: + lda #%00100000 + sta VIA_IER + lda rs_vector + ldx rs_vector+1 + sta IRQVec + stx IRQVec+1 + lda #0 + sta rs_vector + sta rs_vector+1 + clv + bvc @irqtestend