Added base driver code without bit transfer
This commit is contained in:
Gregor Riepl
parent
3f3403eaa3
commit
4a6e099f5f
2 changed files with 440 additions and 0 deletions
12
Makefile
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12
Makefile
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@ -0,0 +1,12 @@
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MACHINE := pet
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.PHONY: all
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all: rs232.bin
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rs232.bin: driver.o
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cl65 -t ${MACHINE} -o $@ $^
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%.o: %.a65
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ca65 -t ${MACHINE} -o $@ $<
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428
driver.a65
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428
driver.a65
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@ -0,0 +1,428 @@
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; 6502 mode
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.p02
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; load useful register/memory locations
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.include "pet.inc"
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; for some reason, the PIA registers are missing in pet.inc...
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PIA1 := $E810
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PIA1_PA := PIA1+$0 ; PORT A or DDR A: Data Direction Register A
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PIA1_CRA := PIA1+$1 ; CRA: Control Register A
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PIA1_PB := PIA1+$2 ; PORT B or DDR B: Data Direction Register B
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PIA1_CRB := PIA1+$3 ; CRB: Control Register B
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PIA2 := $E820
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PIA2_PA := PIA2+$0
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PIA2_CRA := PIA2+$1
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PIA2_PB := PIA2+$2
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PIA2_CRB := PIA2+$3
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; 1MHz phase2 clock
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PHI2_CLOCK = 1000000
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; don't set the baud rate too high, or other operations will be starved
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BAUD_RATE = 300
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; we expect to be loaded somewhere in the middle of user ram
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; TODO verify if this is safe with the Editor/Basic 2.0 ROM
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.org $7000
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; entry points
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.code
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; these are convenience entry points right at the beginning of the page,
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; to reduce dependency on code size.
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; relocatable code would be perfect, but that's a lot more work.
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.export rs_install
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rs_install:
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jmp install
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.export rs_uninstall
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rs_uninstall:
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jmp uninstall
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.export rs_read
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rs_read:
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jmp read
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.export rs_write
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rs_write:
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jmp write
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; parameters and return values
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.data
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; available bytes to read or write
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.export rs_available
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rs_available: .byte 0
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; single byte transfer from input / to output fifo
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.export rs_data
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rs_data: .byte 0
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; status of operation
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rs_status_ok = 0
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rs_status_read_buffer_empty = 1
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rs_status_write_buffer_full = 2
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rs_status_device_not_initialized = 3
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rs_status_device_already_initialized = 4
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.export rs_status
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rs_status: .byte 0
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; driver state data
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; 1=driver initialized
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initialized: .byte 0
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; saved IRQ vector
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oldvector: .word 0
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; current CRA value on CA1 change (bit contains the state of CA1)
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ca1state: .byte 0
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; output buffer
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; this is 16bit, because we need to process start and stop bits as well
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outbuf: .word 0
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; current shifted bit (if 0, no data is being transferred)
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outshift: .byte 0
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; output queue (16 bytes)
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; this is a push from the front - pop from the tail fifo
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outqlen: .byte 0
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outq: .res 16, 0
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; input buffer
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inbuf: .word 0
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; current shifted bit (if 0, no data is being transferred)
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inshift: .byte 0
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; input queue (16 bytes)
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; this is a push from the tail - pop from the front fifo
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inqlen: .byte 0
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inq: .res 16, 0
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; main code follows
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.code
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; driver installation, must be called once to set up IRQs, etc.
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install:
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; check if we're already initialized
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lda initialized
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beq @hwinit
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; signal error
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lda #rs_status_device_already_initialized
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sta rs_status
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; and return
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rts
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@hwinit:
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; disable interrupts, so we're not disturbed
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cli
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; save the previous handler
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lda IRQVec
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sta oldvector
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lda IRQVec+1
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sta oldvector+1
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; assign our custom interrupt handler to the IRQ vector
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lda #>irqhandler
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sta IRQVec
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lda #<irqhandler
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sta IRQVec+1
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; the timer is only started when a transmission is actually initiated
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; but we'll enable VIA timer 1 interrupt
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lda VIA_IER
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ora #%01000000
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sta VIA_IER
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; set up the PIA1 and VIA to process I/O
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; TXD: VIA PB3, output
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lda VIA_DDRB
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ora #%00001000
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sta VIA_DDRB
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; RXD: PIA1 CA1, input, interrupt
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lda PIA1_CRA
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; we start with the negative transition (RS232 start bit: H->L)
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and #%11111101
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; IRQ enable
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ora #%00000001
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sta PIA1_CRA
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; CTS: PIA1 CB2, output (optional)
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; RTS: PIA1 PA4, input (optional)
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; clear some of the state variables
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; the buffers are controlled by other variables anyway and don't need clearing
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lda #0
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sta ca1state
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sta outshift
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sta outqlen
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sta inshift
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sta inqlen
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; we're ready
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lda #1
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sta initialized
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; and ok
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lda #rs_status_ok
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sta rs_status
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; fire away
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sei
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; return
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rts
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; driver uninstallation, must be called once to set up IRQs, etc.
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.export uninstall
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uninstall:
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; check if we're already initialized
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lda initialized
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bne @hwuninit
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; signal error
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lda #rs_status_device_not_initialized
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sta rs_status
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; and return
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rts
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@hwuninit:
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; disable interrupts, so we're not disturbed
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cli
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; restore the previous handler
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lda oldvector
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ldx oldvector+1
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sta IRQVec
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stx IRQVec+1
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; disable all interrupts
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; RXD: PIA1 CA1
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lda PIA1_CRA
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; IRQ disable
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and #%11111110
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sta PIA1_CRA
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; and the VIA timer 1
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lda VIA_IER
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and #%10111111
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sta VIA_IER
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; we leave the I/O pins and the state alone
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; but we'll go back to uninitalized state
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lda #0
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sta initialized
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; and ok
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lda #rs_status_ok
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sta rs_status
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; the rest of the system will probably want interrupts enabled
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sei
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; return
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rts
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; write one byte to FIFO
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.export write
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write:
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; check if we're already initialized
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lda initialized
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bne @dowrite
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; signal error
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lda #rs_status_device_not_initialized
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sta rs_status
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; and return
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rts
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@dowrite:
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; disable interrupts while we write into the buffer
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cli
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; test if there's space in the buffer first
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lda #16
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cmp outqlen
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beq @wrnodata
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; move data up first
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ldy outqlen
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; check if we need to move data at all
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bne @wrbufend
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; move all existing elements up, starting from the top
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@wrbufloop:
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lda outq-1,y
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sta outq,y
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dey
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bne @wrbufloop
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@wrbufend:
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; write data to head
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lda rs_data
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sta outq
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; update queue length
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ldy outqlen
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iny
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sty outqlen
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; also store to return value
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sty rs_available
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; all right
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lda #rs_status_ok
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sta rs_status
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; an unconditional branch would be useful...
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clc
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bcc @wrdone
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@wrnodata:
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; return error
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lda #rs_status_write_buffer_full
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sta rs_status
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@wrdone:
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; and re-enable
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sei
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; return
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rts
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; read one byte from FIFO
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.export read
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read:
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; check if we're already initialized
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lda initialized
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bne @doread
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; signal error
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lda #rs_status_device_not_initialized
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sta rs_status
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; and return
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rts
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@doread:
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; disable interrupts while we read the buffer
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cli
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; test if we have any data first
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lda inqlen
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beq @rdnodata
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; return data from head
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lda inq
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sta rs_data
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; update the queue length
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ldy inqlen
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dey
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sty inqlen
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; also store to return value
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sty rs_available
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; check if we need to move any data
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bne @rdbufend
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; move all other data elements down
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ldx #0
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@rdbufloop:
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lda inq+1,x
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sta inq,x
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inx
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dey
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bne @rdbufloop
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@rdbufend:
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; all right
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lda #rs_status_ok
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sta rs_status
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; an unconditional branch would be useful...
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clc
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bcc @rddone
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@rdnodata:
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; return error
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lda #rs_status_read_buffer_empty
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sta rs_status
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@rddone:
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; and re-enable
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sei
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; return
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rts
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; start the timer
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@starttimer:
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; set up the VIA timer 1 to fire periodically
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period = PHI2_CLOCK/BAUD_RATE
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lda #>period
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sta VIA_T1CL
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lda #<period
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sta VIA_T1CH
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; VIA timer 1 free-run mode
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lda VIA_CR
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ora #%01000000
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sta VIA_CR
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; return
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rts
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; stop the timer
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@stoptimer:
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; VIA timer 1 disabled
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lda VIA_CR
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and #%10111111
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sta VIA_CR
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; return
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rts
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; IRQ handler
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.interruptor irqhandler
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irqhandler:
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; disable interrupts
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cli
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; clear decimal flag to avoid unexpected behavior
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cld
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; save registers
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pha
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txa
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pha
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tya
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pha
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; test for the interrupts we're expecting
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@handleflip:
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; read PIA1 CRA, interrupt flag is automatically cleared
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lda PIA1_CRA
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; save for later, so we don't need to fetch it again
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tax
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; bit 7 is the CA1 interrupt flag - fired?
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and #%10000000
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; nope, skip flip handling
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beq @handletimer
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; handle CA1 interrupt
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; fetch saved CRA
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txa
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; save current value for later use:
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; bit 2 is contains the active value of CA1, which is what we want to know
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sta ca1state
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; invert transition (H->L <-> L->H)
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eor #%00000010
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; mask out interrupt flag - we don't want another IRQ right away
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and #%01111111
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sta PIA1_CRA
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@handletimer:
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; VIA timer 1 fired?
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lda VIA_IFR
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and #%01000000
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; zero, no interrupt
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beq @irqreturn
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; handle timer interrupt
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; reset timer 1 interrupt
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; FIXME should we do this? perhaps someone else is also expecting a VIA interrupt
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; if not, we *must* reset it
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lda VIA_T1CL
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@processfifo:
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; TODO process input and output
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@irqreturn:
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; restore registers
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pla
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tay
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pla
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tax
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pla
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; enable interrupts
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; FIXME should we do this here? what's common practice? is this compatible with other interrupt handlers
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sei
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; jump to previous handler
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; we don't need to return or restore flags, this will be done by the chained interrupt handler
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jmp (oldvector)
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