; 6502 mode
.p02

; load useful register/memory locations
.include "pet.inc"

; for some reason, the PIA registers are missing in pet.inc...
PIA1 := $E810
PIA1_PA  := PIA1+$0 ; PORT A or DDR A: Data Direction Register A
PIA1_CRA := PIA1+$1 ; CRA: Control Register A
PIA1_PB  := PIA1+$2 ; PORT B or DDR B: Data Direction Register B
PIA1_CRB := PIA1+$3 ; CRB: Control Register B
PIA2 := $E820
PIA2_PA  := PIA2+$0
PIA2_CRA := PIA2+$1
PIA2_PB  := PIA2+$2
PIA2_CRB := PIA2+$3

; 1MHz phase2 clock
PHI2_CLOCK = 1000000
; don't set the baud rate too high, or other operations will be starved
BAUD_RATE = 600

; parameters and return values can reside in an unused area of the zero page
.zeropage
	; used as the shift register counter
	.export rs_available
	rs_available: .byte 0
	; shift register
	.export rs_data
	rs_data: .word 0
	; saved old interrupt vector
	.export rs_vector
	rs_vector: .word 0

; this is for the load address, so we can generate PRG files.
; works as long as the code segment comes right after these two bytes,
; i.e. as long as the LOADADDR segment resides at $load_address - 2
.segment "LOADADDR"
	.export LOADADDR
	LOADADDR:
	.word *+2

; test code follows
.code

	; test code:
	; single-byte RS-232 transmission
	; this code runs asynchronously in a VIA T2 interrupt handler
	; the handler is installed and uninstalled automatically until
	; transmission is complete.
	; do not call this too quickly in succession, or you will lock
	; up the CPU in an endless loop.

	testperiod = PHI2_CLOCK/BAUD_RATE

	test:
		sei

		lda IRQVec
		cmp irqtest
		bne @testok
		lda IRQVec+1
		cmp irqtest+1
		beq @testend

	@testok:
		lda #10
		sta rs_available
		lda rs_data
		asl a
		sta rs_data
		lda #%00000001
		rol a
		sta rs_data+1

		lda VIA_DDRB
		ora #%00001000
		sta VIA_DDRB

		lda IRQVec
		ldx IRQVec+1
		sta rs_vector
		stx rs_vector+1
		lda #<irqtest
		ldx #>irqtest
		sta IRQVec
		stx IRQVec+1

		lda VIA_CR
		and #%11011111
		sta VIA_CR
		lda #%10100000
		sta VIA_IER
		lda #<testperiod
		ldx #>testperiod
		sta VIA_T2CL
		stx VIA_T2CH

	@testend:
		cli
		rts

	irqtest:
		sei
		cld
		pha
		txa
		pha

		lda VIA_IFR
		and #%00100000
		beq @irqtestend

		ldx rs_available
		beq @irqtestrestore
		dex
		stx rs_available

		;lda #<testperiod
		ldx #>testperiod
		;sta VIA_T2CL
		stx VIA_T2CH

		lsr rs_data+1
		ror rs_data
		lda VIA_PB
		bcc @irqtestblank
		ora #%00001000
		bcs @irqtestwrite
	@irqtestblank:
		and #%11110111
	@irqtestwrite:
		sta VIA_PB

	@irqtestend:
		pla
		tax
		pla
		jmp (rs_vector)

	@irqtestrestore:
		lda #%00100000
		sta VIA_IER
		lda rs_vector
		ldx rs_vector+1
		sta IRQVec
		stx IRQVec+1
		lda #0
		sta rs_vector
		sta rs_vector+1
		clv
		bvc @irqtestend