Gregor Riepl
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7f742b2021
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Added module library
Fixed up schema with new part names
Partial PCB redesign, incorporated schematic changes and errata
Made PCB slightly smaller
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2015-04-05 13:57:04 +02:00 |
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Gregor Riepl
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2927c833ac
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Updated schematic revision and copyright
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2015-04-03 18:15:04 +02:00 |
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Gregor Riepl
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78d82c87f2
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Fixed banknote scanner connector erratum, short circuit on power lines
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2015-04-03 18:12:38 +02:00 |
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Gregor Riepl
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3928ebaa2f
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Added component library
Updated conmponents in schematic
Changed resistors and capacitors to standard symbol
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2015-04-03 18:09:41 +02:00 |
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Gregor Riepl
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6db273f22e
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Fixed a number of errata in first control board revision
Swapped USB B port D+ and D- lines
Swapped UART0 RX and TX lines
Changed resistor values
Added UART0 RX and TX LEDs
Conntected USB sleep control line
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2015-04-02 18:17:12 +02:00 |
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Gregor Riepl
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d71b00987a
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Added redesigned control board schema and PCB layout
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2015-04-02 17:54:58 +02:00 |
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