Gregor Riepl
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a70d759aef
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Finetuning
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2024-09-29 12:45:00 +02:00 |
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Gregor Riepl
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ba983ad9da
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Removed some extras and finished routing PCB
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2024-09-28 22:15:21 +02:00 |
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Gregor Riepl
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b1dd0f0aaf
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Added UART lib ROM, addr logic and placed ICs
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2024-09-09 12:35:14 +02:00 |
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Gregor Riepl
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9229cef954
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Drop excluded parts from BOM
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2024-09-04 07:46:42 +02:00 |
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Gregor Riepl
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d3379170c1
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Refresh schema and PCB, remove obsolete sections
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2024-09-04 07:33:55 +02:00 |
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Gregor Riepl
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e6ca30ddba
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Routed 62c2256 RAM, added speaker
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2024-03-13 08:19:07 +01:00 |
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Gregor Riepl
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ae654de79a
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wip v4 variant
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2024-03-10 14:44:15 +01:00 |
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Gregor Riepl
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5ab7d36e3a
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Group blocks in schematic
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2024-03-10 13:30:34 +01:00 |
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Gregor Riepl
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b814979dab
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CE should depend on phi2
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2024-03-06 23:56:51 +01:00 |
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Gregor Riepl
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1a9320a034
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Add test points, reorder reset header
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2024-03-02 23:58:15 +01:00 |
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Gregor Riepl
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aab0e2b974
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Added pulse generator to WR pin
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2024-02-08 01:32:12 +01:00 |
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Gregor Riepl
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01487a4c75
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Correct pinout for PET mem interface
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2023-11-12 21:51:37 +01:00 |
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Gregor Riepl
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286b80476c
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Enlarged vias for cnc production
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2023-10-17 23:43:20 +02:00 |
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Gregor Riepl
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741f704ef9
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Initial checkin
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2023-10-13 09:27:04 +02:00 |
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