Gregor Riepl
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ba983ad9da
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Removed some extras and finished routing PCB
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2024-09-28 22:15:21 +02:00 |
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Gregor Riepl
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b1dd0f0aaf
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Added UART lib ROM, addr logic and placed ICs
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2024-09-09 12:35:14 +02:00 |
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Gregor Riepl
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cb53088da3
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Revert back to SOP-28
This reverts commit e915f888f8.
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2024-09-06 09:22:57 +02:00 |
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Gregor Riepl
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e915f888f8
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PCB with DIP-28 SRAM
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2024-09-06 09:21:51 +02:00 |
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Gregor Riepl
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9229cef954
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Drop excluded parts from BOM
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2024-09-04 07:46:42 +02:00 |
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Gregor Riepl
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d3379170c1
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Refresh schema and PCB, remove obsolete sections
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2024-09-04 07:33:55 +02:00 |
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Gregor Riepl
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e6ca30ddba
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Routed 62c2256 RAM, added speaker
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2024-03-13 08:19:07 +01:00 |
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Gregor Riepl
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ae654de79a
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wip v4 variant
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2024-03-10 14:44:15 +01:00 |
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Gregor Riepl
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5ab7d36e3a
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Group blocks in schematic
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2024-03-10 13:30:34 +01:00 |
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Gregor Riepl
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aaa309abfe
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Add HCT10 option to reduce propagation delay
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2024-03-09 11:22:57 +01:00 |
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Gregor Riepl
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b814979dab
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CE should depend on phi2
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2024-03-06 23:56:51 +01:00 |
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Gregor Riepl
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1a9320a034
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Add test points, reorder reset header
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2024-03-02 23:58:15 +01:00 |
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Gregor Riepl
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68d7e86e99
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Layout
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2024-02-08 01:33:47 +01:00 |
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Gregor Riepl
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aab0e2b974
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Added pulse generator to WR pin
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2024-02-08 01:32:12 +01:00 |
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Gregor Riepl
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30086b7cfd
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Update sheet versions
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2023-11-12 21:53:52 +01:00 |
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Gregor Riepl
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01487a4c75
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Correct pinout for PET mem interface
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2023-11-12 21:51:37 +01:00 |
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Gregor Riepl
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b484a0842c
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Add sheet descriptions, make some vias more accessible
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2023-10-13 21:22:23 +02:00 |
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Gregor Riepl
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22778fce4f
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Designate power connector same as on main board
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2023-10-13 14:08:04 +02:00 |
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Gregor Riepl
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e20ca7fe49
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Add 5V regulator
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2023-10-13 14:04:56 +02:00 |
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Gregor Riepl
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5f8c386c82
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Gate out A15
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2023-10-13 11:53:55 +02:00 |
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Gregor Riepl
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adcadc5eec
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Relayout to reduce crossing
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2023-10-13 11:04:36 +02:00 |
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Gregor Riepl
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741f704ef9
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Initial checkin
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2023-10-13 09:27:04 +02:00 |
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