659 lines
12 KiB
Text
659 lines
12 KiB
Text
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; 6502 mode
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.p02
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; load useful register/memory locations
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.include "pet.inc"
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; for some reason, the PIA registers are missing in pet.inc...
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PIA1 := $E810
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PIA1_PA := PIA1+$0 ; PORT A or DDR A: Data Direction Register A
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PIA1_CRA := PIA1+$1 ; CRA: Control Register A
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PIA1_PB := PIA1+$2 ; PORT B or DDR B: Data Direction Register B
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PIA1_CRB := PIA1+$3 ; CRB: Control Register B
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PIA2 := $E820
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PIA2_PA := PIA2+$0
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PIA2_CRA := PIA2+$1
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PIA2_PB := PIA2+$2
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PIA2_CRB := PIA2+$3
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; 1MHz phase2 clock
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PHI2_CLOCK = 1000000
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; don't set the baud rate too high, or other operations will be starved
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BAUD_RATE = 600
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; parameters and return values can reside in an unused area of the zero page
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.zeropage
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; available bytes to read or write
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.export rs_available
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rs_available: .byte 0
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; single byte transfer from input / to output fifo
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.export rs_data
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rs_data: .byte 0
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; status of operation
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rs_status_ok = 0
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rs_status_read_buffer_empty = 1
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rs_status_write_buffer_full = 2
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rs_status_device_not_initialized = 3
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rs_status_device_already_initialized = 4
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.export rs_status
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rs_status: .byte 0
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; TODO add a state variable that can be monitored by the BASIC WAIT command
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; this is for the load address, so we can generate PRG files.
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; works as long as the code segment comes right after these two bytes,
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; i.e. as long as the LOADADDR segment resides at $load_address - 2
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.segment "LOADADDR"
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.export LOADADDR
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LOADADDR:
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.word *+2
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; entry points
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.code
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; for development and testing
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.export rs_test
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rs_test:
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jmp test
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; these are convenience entry points right at the beginning of the page,
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; to reduce dependency on code size.
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; relocatable code would be perfect, but that's a lot more work.
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.export rs_install
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rs_install:
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jmp install
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.export rs_uninstall
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rs_uninstall:
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jmp uninstall
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.export rs_read
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rs_read:
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jmp read
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.export rs_write
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rs_write:
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jmp write
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; driver state data
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.bss
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; 1=driver initialized
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initialized: .byte 0
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; saved IRQ vector
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oldvector: .word 0
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; state of the CA1 input: bit2=0 low level, bit2=1 high level
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ca1state: .byte 0
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; output buffer
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; this is 16bit, because we need to process start and stop bits as well
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outbuf: .word 0
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; current shifted bit (if 0, no data is being transferred)
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outshift: .byte 0
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; output queue (16 bytes)
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; this is a push from the front - pop from the tail fifo
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outqlen: .byte 0
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outq: .res 16, 0
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; input buffer
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inbuf: .word 0
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; current shifted bit (if 0, no data is being transferred)
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inshift: .byte 0
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; input queue (16 bytes)
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; this is a push from the tail - pop from the front fifo
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inqlen: .byte 0
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inq: .res 16, 0
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; main code follows
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.code
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;FIXME BEGIN
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; test code:
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; single-byte RS-232 transmission
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; this code runs asynchronously in a VIA T2 interrupt handler
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; the handler is installed and uninstalled automatically until
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; transmission is complete.
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; do not call this too quickly in succession, or you will lock
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; up the CPU in an endless loop.
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test:
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sei
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lda #10
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sta rs_available
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lda rs_data
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asl a
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sta rs_data
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lda #%00000001
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rol a
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sta rs_data+1
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lda VIA_DDRB
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ora #%00001000
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sta VIA_DDRB
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lda IRQVec
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ldx IRQVec+1
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sta oldvector
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stx oldvector+1
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lda #<irqtest
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ldx #>irqtest
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sta IRQVec
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stx IRQVec+1
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lda VIA_CR
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and #%11011111
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sta VIA_CR
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lda #%10100000
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sta VIA_IER
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testperiod = PHI2_CLOCK/BAUD_RATE
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lda #<testperiod
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ldx #>testperiod
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sta VIA_T2CL
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stx VIA_T2CH
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rts
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cli
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rts
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irqtest:
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sei
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cld
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pha
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txa
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pha
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lda VIA_IFR
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and #%00100000
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beq @irqtestend
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ldx rs_available
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beq @irqtestrestore
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dex
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stx rs_available
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;lda #<testperiod
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ldx #>testperiod
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;sta VIA_T2CL
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stx VIA_T2CH
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lsr rs_data+1
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ror rs_data
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lda VIA_PB
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bcc @irqtestblank
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ora #%00001000
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bcs @irqtestwrite
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@irqtestblank:
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and #%11110111
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@irqtestwrite:
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sta VIA_PB
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@irqtestend:
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pla
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tax
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pla
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jmp (oldvector)
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@irqtestrestore:
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lda #%00100000
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sta VIA_IER
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lda oldvector
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ldx oldvector+1
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sta IRQVec
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stx IRQVec+1
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clv
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bvc @irqtestend
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;FIXME END
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; driver installation, must be called once to set up IRQs, etc.
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install:
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; FIXME this doesn't work if we're loading from ROM
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lda #1
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sta initialized
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; check if we're already initialized
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lda initialized
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beq @hwinit
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; signal error
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lda #rs_status_device_already_initialized
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sta rs_status
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; and return
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rts
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@hwinit:
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; disable interrupts, so we're not disturbed
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sei
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; save the previous handler
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lda IRQVec
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sta oldvector
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lda IRQVec+1
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sta oldvector+1
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; assign our custom interrupt handler to the IRQ vector
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lda #<irqhandler
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sta IRQVec
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lda #>irqhandler
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sta IRQVec+1
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; VIA timer 2 cannot be enabled and disabled on the fly, so we'll
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; configure it here and arm it later
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; one-shot mode
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lda VIA_CR
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and #%11011111
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sta VIA_CR
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; enable interrupt
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; interrupt enable is done by setting bit7 and the desired interrupt
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; bit in IER to 1 (no need to read-modify-write)
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lda #%10100000
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sta VIA_IER
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; set up the PIA1 and VIA to process I/O
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; TXD: VIA PB3, output
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lda VIA_DDRB
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ora #%00001000
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sta VIA_DDRB
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; RXD: PIA1 CA1, input, interrupt
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lda PIA1_CRA
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; we start with the negative transition (RS232 start bit: H->L)
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and #%11111101
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; IRQ enable
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ora #%00000001
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sta PIA1_CRA
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; CTS: PIA1 CB2, output (optional)
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; RTS: PIA1 PA4, input (optional)
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; clear some of the state variables
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; the buffers are controlled by other variables anyway and don't need clearing
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lda #0
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sta ca1state
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sta outshift
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sta outqlen
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sta inshift
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sta inqlen
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; we're ready
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lda #1
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sta initialized
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; and ok
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lda #rs_status_ok
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sta rs_status
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; fire away
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cli
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; return
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rts
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; driver uninstallation, must be called once to set up IRQs, etc.
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.export uninstall
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uninstall:
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; check if we're already initialized
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lda initialized
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bne @hwuninit
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; signal error
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lda #rs_status_device_not_initialized
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sta rs_status
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; and return
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rts
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@hwuninit:
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; disable interrupts, so we're not disturbed
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sei
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; restore the previous handler
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lda oldvector
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ldx oldvector+1
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sta IRQVec
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stx IRQVec+1
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; disable all interrupts
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; RXD: PIA1 CA1
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lda PIA1_CRA
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; IRQ disable
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and #%11111110
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sta PIA1_CRA
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; and the VIA timer 2
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; clearing is done by setting bit 7 to 0 and the desired interrupt to 1
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lda #%00100000
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sta VIA_IER
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; we leave the I/O pins and the state alone
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; but we'll go back to uninitalized state
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lda #0
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sta initialized
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; and ok
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lda #rs_status_ok
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sta rs_status
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; the rest of the system will probably want interrupts enabled
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cli
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; return
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rts
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; write one byte to FIFO
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.export write
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write:
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; check if we're already initialized
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lda initialized
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bne @dowrite
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; signal error
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lda #rs_status_device_not_initialized
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sta rs_status
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; and return
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rts
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@dowrite:
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; disable interrupts while we write into the buffer
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sei
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; test if there's space in the buffer first
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lda #16
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cmp outqlen
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beq @wrnodata
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; move data up first
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ldy outqlen
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; check if we need to move data at all
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bne @wrbufend
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; move all existing elements up, starting from the top
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@wrbufloop:
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lda outq-1,y
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sta outq,y
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dey
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bne @wrbufloop
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@wrbufend:
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; write data to head
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lda rs_data
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sta outq
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; update queue length
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ldy outqlen
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iny
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sty outqlen
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; also store to return value
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sty rs_available
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; all right
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lda #rs_status_ok
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sta rs_status
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; an unconditional branch would be useful...
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clc
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bcc @wrdone
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@wrnodata:
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; return error
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lda #rs_status_write_buffer_full
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sta rs_status
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@wrdone:
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; and re-enable
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cli
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; return
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rts
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; read one byte from FIFO
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.export read
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read:
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; check if we're already initialized
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lda initialized
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bne @doread
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; signal error
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lda #rs_status_device_not_initialized
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sta rs_status
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; and return
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rts
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@doread:
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; disable interrupts while we read the buffer
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sei
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; test if we have any data first
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lda inqlen
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beq @rdnodata
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; return data from head
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lda inq
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sta rs_data
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; update the queue length
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ldy inqlen
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dey
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sty inqlen
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; also store to return value
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sty rs_available
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; check if we need to move any data
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bne @rdbufend
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; move all other data elements down
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ldx #0
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@rdbufloop:
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lda inq+1,x
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sta inq,x
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inx
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dey
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bne @rdbufloop
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@rdbufend:
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; all right
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lda #rs_status_ok
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sta rs_status
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; an unconditional branch would be useful...
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clc
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bcc @rddone
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@rdnodata:
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; return error
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lda #rs_status_read_buffer_empty
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sta rs_status
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@rddone:
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; and re-enable
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cli
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; return
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rts
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; start the timer
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starttimer:
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; arm VIA timer 2 by latching the counter
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period = PHI2_CLOCK/BAUD_RATE
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lda #<period
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sta VIA_T1CL
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lda #>period
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sta VIA_T1CH
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; return
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rts
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; stop the timer
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@stoptimer:
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; VIA timer 1 disabled
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lda VIA_CR
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and #%10111111
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sta VIA_CR
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; return
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rts
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; IRQ handler
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.interruptor irqhandler
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irqhandler:
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; disable interrupts
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sei
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; clear decimal flag to avoid unexpected behavior
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cld
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; save registers
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pha
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txa
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pha
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tya
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pha
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; test for the interrupts we're expecting
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@handleflip:
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; read PIA1 CRA, interrupt flag is automatically cleared
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lda PIA1_CRA
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; save CRA for later, so we don't need to fetch it again
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tax
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; bit 7 is the CA1 interrupt flag - fired?
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and #%10000000
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; nope, skip flip handling
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beq @handletimer
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; handle CA1 interrupt
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; fetch saved CRA
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txa
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; save current value for later use:
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; bit 2 is contains the active value of CA1, which is what we want to know
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sta ca1state
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; invert transition (H->L <-> L->H)
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eor #%00000010
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; mask out interrupt flag - we don't want another IRQ right away
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and #%01111111
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sta PIA1_CRA
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; check if we're already in the middle of a reception
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lda inshift
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; yes, don't do anything
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bne @handletimer
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; nope, initiate reception
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lda #10
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sta inshift
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@handletimer:
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; VIA timer 2 fired?
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lda VIA_IFR
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and #%00100000
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; zero, no interrupt
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beq @irqreturn
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; timer 2 fired: rearm (we're in one-shot mode!), and clear the interrupt flag
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; FIXME this should be done earlier, for more accurate timing
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; FIXME we could skip writing the low byte here, writing the high byte is enough
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jsr starttimer
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@loadout:
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; do we have more bits to send?
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lda outshift
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; yes, skip loading next byte
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bne @shiftout
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; load next byte from FIFO
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; do we have more bytes?
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lda outqlen
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; nope, skip ahead to input processing
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beq @shiftin
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; load length
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ldx outqlen
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; decrement, also gives the index
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dex
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; load next byte from fifo
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lda outq,x
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; store new queue length
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stx outqlen
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; prepare shift register
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; layout: 000000E7 6543210S
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; bit0 = start bit = 0
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; bit1..7 = data0..6
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clc
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rol
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sta outbuf
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; bit8 = data7
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; bit9 = stop bit = 1
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lda #%00000001
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rol
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sta outbuf+1
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; we're shifting 10 bits out
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lda #10
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sta outshift
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@shiftout:
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; make sure overflow flag is clear, so we can do unconditional branches
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clv
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; load shift register bit 0
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lda outbuf
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and #%00000001
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; mark or blank?
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beq @shiftoutblank
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; set output high
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lda #%00001000
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ora VIA_PB
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bvc @shiftoutstore
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@shiftoutblank:
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; set output low
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lda #%11110111
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and VIA_PB
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@shiftoutstore:
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sta VIA_PB
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; shift the next bit in
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; 0 -> high byte -> carry
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lsr outbuf+1
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; carry -> low byte
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ror outbuf
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; decrement counter
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dec outshift
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@shiftin:
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; FIXME we should check the start and stop bits, to synchronize RS232 transmissions
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; check first if a reception is in progress
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lda inshift
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; nope, skip input processing
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beq @irqreturn
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; for unconditional branch
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clv
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; pick up the current CA1 state
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lda ca1state
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and #%00000100
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; mark or blank?
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beq @shiftinblank
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; shift in high bit
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sec
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bvc @shiftinstore
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@shiftinblank:
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; shift in low bit
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clc
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@shiftinstore:
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; rotate carry bit into buffer
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rol inbuf
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rol inbuf+1
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; decrement counter
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dec inshift
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@storein:
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; did we complete a transmission?
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bne @irqreturn
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|
; check if we have space available in the buffer
|
|
lda inqlen
|
|
cmp #16
|
|
; nope, drop this byte
|
|
bcc @irqreturn
|
|
|
|
; yes, store it
|
|
tax
|
|
lda inbuf+1
|
|
lsr
|
|
lda inbuf
|
|
ror
|
|
sta inq, x
|
|
|
|
; and update the buffer length
|
|
dex
|
|
stx inqlen
|
|
|
|
@irqreturn:
|
|
; restore registers
|
|
pla
|
|
tay
|
|
pla
|
|
tax
|
|
pla
|
|
; we don't need to re-enable interrupts here,
|
|
; this will happen automatically when flags are restored later
|
|
;cli
|
|
; jump to previous handler
|
|
; we don't need to return or restore flags, this will be done by the chained interrupt handler
|
|
jmp (oldvector)
|