Split out test driver into driver2
This commit is contained in:
Gregor Riepl
parent
2ccb2f9a5d
commit
2ebbbd7468
2 changed files with 154 additions and 101 deletions
101
driver.a65
101
driver.a65
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@ -50,10 +50,6 @@ BAUD_RATE = 600
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; entry points
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.code
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; for development and testing
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.export rs_test
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rs_test:
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jmp test
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; these are convenience entry points right at the beginning of the page,
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; to reduce dependency on code size.
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; relocatable code would be perfect, but that's a lot more work.
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@ -99,103 +95,6 @@ BAUD_RATE = 600
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; main code follows
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.code
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;FIXME BEGIN
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; test code:
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; single-byte RS-232 transmission
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; this code runs asynchronously in a VIA T2 interrupt handler
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; the handler is installed and uninstalled automatically until
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; transmission is complete.
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; do not call this too quickly in succession, or you will lock
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; up the CPU in an endless loop.
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test:
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sei
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lda #10
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sta rs_available
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lda rs_data
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asl a
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sta rs_data
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lda #%00000001
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rol a
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sta rs_data+1
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lda VIA_DDRB
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ora #%00001000
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sta VIA_DDRB
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lda IRQVec
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ldx IRQVec+1
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sta oldvector
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stx oldvector+1
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lda #<irqtest
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ldx #>irqtest
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sta IRQVec
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stx IRQVec+1
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lda VIA_CR
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and #%11011111
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sta VIA_CR
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lda #%10100000
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sta VIA_IER
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testperiod = PHI2_CLOCK/BAUD_RATE
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lda #<testperiod
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ldx #>testperiod
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sta VIA_T2CL
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stx VIA_T2CH
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rts
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cli
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rts
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irqtest:
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sei
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cld
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pha
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txa
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pha
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lda VIA_IFR
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and #%00100000
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beq @irqtestend
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ldx rs_available
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beq @irqtestrestore
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dex
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stx rs_available
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;lda #<testperiod
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ldx #>testperiod
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;sta VIA_T2CL
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stx VIA_T2CH
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lsr rs_data+1
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ror rs_data
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lda VIA_PB
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bcc @irqtestblank
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ora #%00001000
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bcs @irqtestwrite
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@irqtestblank:
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and #%11110111
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@irqtestwrite:
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sta VIA_PB
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@irqtestend:
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pla
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tax
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pla
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jmp (oldvector)
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@irqtestrestore:
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lda #%00100000
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sta VIA_IER
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lda oldvector
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ldx oldvector+1
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sta IRQVec
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stx IRQVec+1
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clv
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bvc @irqtestend
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;FIXME END
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; driver installation, must be called once to set up IRQs, etc.
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install:
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; FIXME this doesn't work if we're loading from ROM
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154
driver2.a65
Normal file
154
driver2.a65
Normal file
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@ -0,0 +1,154 @@
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; 6502 mode
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.p02
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; load useful register/memory locations
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.include "pet.inc"
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; for some reason, the PIA registers are missing in pet.inc...
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PIA1 := $E810
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PIA1_PA := PIA1+$0 ; PORT A or DDR A: Data Direction Register A
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PIA1_CRA := PIA1+$1 ; CRA: Control Register A
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PIA1_PB := PIA1+$2 ; PORT B or DDR B: Data Direction Register B
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PIA1_CRB := PIA1+$3 ; CRB: Control Register B
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PIA2 := $E820
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PIA2_PA := PIA2+$0
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PIA2_CRA := PIA2+$1
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PIA2_PB := PIA2+$2
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PIA2_CRB := PIA2+$3
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; 1MHz phase2 clock
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PHI2_CLOCK = 1000000
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; don't set the baud rate too high, or other operations will be starved
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BAUD_RATE = 600
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; parameters and return values can reside in an unused area of the zero page
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.zeropage
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; used as the shift register counter
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.export rs_available
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rs_available: .byte 0
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; shift register
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.export rs_data
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rs_data: .word 0
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; saved old interrupt vector
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.export rs_vector
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rs_vector: .word 0
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; this is for the load address, so we can generate PRG files.
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; works as long as the code segment comes right after these two bytes,
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; i.e. as long as the LOADADDR segment resides at $load_address - 2
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.segment "LOADADDR"
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.export LOADADDR
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LOADADDR:
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.word *+2
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; test code follows
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.code
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; test code:
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; single-byte RS-232 transmission
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; this code runs asynchronously in a VIA T2 interrupt handler
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; the handler is installed and uninstalled automatically until
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; transmission is complete.
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; do not call this too quickly in succession, or you will lock
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; up the CPU in an endless loop.
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testperiod = PHI2_CLOCK/BAUD_RATE
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test:
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sei
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lda IRQVec
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cmp irqtest
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bne @testok
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lda IRQVec+1
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cmp irqtest+1
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beq @testend
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@testok:
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lda #10
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sta rs_available
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lda rs_data
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asl a
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sta rs_data
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lda #%00000001
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rol a
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sta rs_data+1
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lda VIA_DDRB
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ora #%00001000
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sta VIA_DDRB
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lda IRQVec
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ldx IRQVec+1
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sta rs_vector
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stx rs_vector+1
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lda #<irqtest
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ldx #>irqtest
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sta IRQVec
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stx IRQVec+1
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lda VIA_CR
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and #%11011111
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sta VIA_CR
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lda #%10100000
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sta VIA_IER
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lda #<testperiod
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ldx #>testperiod
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sta VIA_T2CL
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stx VIA_T2CH
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@testend:
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cli
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rts
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irqtest:
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sei
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cld
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pha
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txa
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pha
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lda VIA_IFR
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and #%00100000
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beq @irqtestend
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ldx rs_available
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beq @irqtestrestore
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dex
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stx rs_available
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;lda #<testperiod
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ldx #>testperiod
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;sta VIA_T2CL
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stx VIA_T2CH
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lsr rs_data+1
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ror rs_data
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lda VIA_PB
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bcc @irqtestblank
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ora #%00001000
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bcs @irqtestwrite
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@irqtestblank:
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and #%11110111
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@irqtestwrite:
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sta VIA_PB
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@irqtestend:
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pla
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tax
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pla
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jmp (rs_vector)
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@irqtestrestore:
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lda #%00100000
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sta VIA_IER
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lda rs_vector
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ldx rs_vector+1
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sta IRQVec
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stx IRQVec+1
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lda #0
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sta rs_vector
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sta rs_vector+1
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clv
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bvc @irqtestend
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