Commit graph

4 commits

Author SHA1 Message Date
Gregor Riepl
88a009d44e Route everything through the inverters for buffering 2022-07-24 22:57:11 +02:00
Gregor Riepl
f5142090f9 Added cassette #2 pins 2022-07-24 22:56:44 +02:00
Gregor Riepl
5e7c5b1bc9 Added link to programming info 2022-07-21 22:42:22 +02:00
Gregor Riepl
445f343a45 Added circuit with inverters 2022-07-21 22:36:35 +02:00