petwifi

seto/petwifi

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4469010fb1 Update patch, better timing info master Gregor Riepl 2022-09-04 10:24:01 +0200
f1d23b090f Rework PCB routing for easier manufacturing Gregor Riepl 2022-09-04 10:03:22 +0200
d73794901f Ignore rom files Gregor Riepl 2022-09-04 10:02:41 +0200
2ebbbd7468 Split out test driver into driver2 Gregor Riepl 2022-09-04 10:02:27 +0200
2ccb2f9a5d Add ROM image generation Gregor Riepl 2022-09-04 10:02:06 +0200
3a59b292a4 Update patch, add basic test prg, rewrite TX test code Gregor Riepl 2022-08-27 15:54:06 +0200
42b1c29509 Added VICE emulation patch Gregor Riepl 2022-08-22 19:10:11 +0200
9f2054453d Generate a PRG file Gregor Riepl 2022-08-22 19:00:42 +0200
9c71e8bbb0 Write state to unused tape buffer Gregor Riepl 2022-08-20 20:31:48 +0200
5508e77589 Add example basic prg Gregor Riepl 2022-08-20 20:26:02 +0200
71d7461031 Fix readme format Gregor Riepl 2022-08-20 18:49:50 +0200
c9bc6b9207 Describe driver interface in readme Gregor Riepl 2022-08-20 18:29:20 +0200
c5a211a8f0 Reconfig memory Gregor Riepl 2022-08-20 17:37:42 +0200
523c4c6dea Implement RX Gregor Riepl 2022-08-20 11:11:19 +0200
14cff310b7 Custom memory config Gregor Riepl 2022-08-19 22:38:18 +0200
83cfce2960 Use VIA T2, implment output Gregor Riepl 2022-08-19 15:03:38 +0200
4a6e099f5f Added base driver code without bit transfer Gregor Riepl 2022-08-13 20:45:08 +0200
3f3403eaa3 Ignore built files Gregor Riepl 2022-08-13 20:44:41 +0200
55962c187b Describe RS232 signal Gregor Riepl 2022-08-13 20:43:52 +0200
14a7a09438 Added mounting holes Gregor Riepl 2022-08-13 20:43:40 +0200
c2c2e50f79 Reorganize routing Gregor Riepl 2022-07-25 23:59:44 +0200
88a009d44e Route everything through the inverters for buffering Gregor Riepl 2022-07-24 22:57:11 +0200
f5142090f9 Added cassette #2 pins Gregor Riepl 2022-07-24 22:56:44 +0200
5e7c5b1bc9 Added link to programming info Gregor Riepl 2022-07-21 22:42:22 +0200
445f343a45 Added circuit with inverters Gregor Riepl 2022-07-21 22:36:35 +0200