Gregor Riepl
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2ccb2f9a5d
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Add ROM image generation
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2022-09-04 10:02:06 +02:00 |
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Gregor Riepl
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3a59b292a4
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Update patch, add basic test prg, rewrite TX test code
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2022-08-27 15:54:06 +02:00 |
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Gregor Riepl
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42b1c29509
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Added VICE emulation patch
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2022-08-22 19:10:11 +02:00 |
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Gregor Riepl
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9f2054453d
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Generate a PRG file
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2022-08-22 19:00:42 +02:00 |
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Gregor Riepl
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9c71e8bbb0
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Write state to unused tape buffer
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2022-08-20 20:31:48 +02:00 |
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Gregor Riepl
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5508e77589
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Add example basic prg
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2022-08-20 20:26:02 +02:00 |
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Gregor Riepl
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71d7461031
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Fix readme format
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2022-08-20 18:49:50 +02:00 |
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Gregor Riepl
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c9bc6b9207
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Describe driver interface in readme
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2022-08-20 18:29:20 +02:00 |
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Gregor Riepl
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c5a211a8f0
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Reconfig memory
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2022-08-20 17:37:42 +02:00 |
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Gregor Riepl
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523c4c6dea
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Implement RX
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2022-08-20 11:11:47 +02:00 |
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Gregor Riepl
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14cff310b7
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Custom memory config
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2022-08-19 22:38:18 +02:00 |
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Gregor Riepl
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83cfce2960
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Use VIA T2, implment output
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2022-08-19 15:03:38 +02:00 |
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Gregor Riepl
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4a6e099f5f
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Added base driver code without bit transfer
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2022-08-13 20:45:08 +02:00 |
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Gregor Riepl
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3f3403eaa3
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Ignore built files
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2022-08-13 20:44:41 +02:00 |
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Gregor Riepl
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55962c187b
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Describe RS232 signal
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2022-08-13 20:43:52 +02:00 |
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Gregor Riepl
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14a7a09438
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Added mounting holes
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2022-08-13 20:43:40 +02:00 |
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Gregor Riepl
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c2c2e50f79
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Reorganize routing
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2022-07-25 23:59:44 +02:00 |
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Gregor Riepl
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88a009d44e
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Route everything through the inverters for buffering
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2022-07-24 22:57:11 +02:00 |
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Gregor Riepl
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f5142090f9
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Added cassette #2 pins
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2022-07-24 22:56:44 +02:00 |
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Gregor Riepl
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5e7c5b1bc9
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Added link to programming info
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2022-07-21 22:42:22 +02:00 |
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Gregor Riepl
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445f343a45
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Added circuit with inverters
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2022-07-21 22:36:35 +02:00 |
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